How I Learnt UVM : A Practical guide
An overview of how I approached learning the UVM concepts and frameworks in a more applied, practical manor.
Hi, i'm
Toby Wright
Electronic Engineering Student
I'm a 2nd-year university student passionate about Digital design and verification - with a focus on IC Design and FPGA engineering in SystemVerilog.
Featured Projects
SystemVerilog
RV32I
RISC-V 32I single cycle processor with 32 general purpose registers and a 32-bit datapath. Designed and verified in SystemVerilog.
SystemVerilog
OOP / CRV
Successive approximation register analog-to-digital convertor in SystemVerilog, with a CRV OOP test environment for boundary-condition testing.
Python
Log file parser, designed to extract erros, warnings and timing analysis from Vivado simulation / synthesis log files.
SystemVerilog
Python
UART
A register debugger for viewing / editing register values on an FPGA over uart using a python CLI.
Blog Posts
Oct 12, 2026