Overview
This project involved designing a single-cycle RISC-V 32I processor from scratch using SystemVerilog. The core includes 32 general-purpose registers, a complete 32-bit datapath, and has 10 core operations implemented.
Instruction Set Architecture (Subset)
| Instruction | Type | Exact Data Structure (Bits [31:0]) | RTL Operation |
|---|---|---|---|
| ADD | R-Type |
0000000
funct7 rs2 src2 rs1 src1 000 funct3 rd dest 0110011 opcode |
R[rd] = R[rs1] + R[rs2] |
| SUB | R-Type |
0100000
funct7 rs2 src2 rs1 src1 000 funct3 rd dest 0110011 opcode |
R[rd] = R[rs1] - R[rs2] |
| AND | R-Type |
0000000
funct7 rs2 src2 rs1 src1 111 funct3 rd dest 0110011 opcode |
R[rd] = R[rs1] & R[rs2] |
| ADDI | I-Type |
imm[11:0]
imm (12) rs1 src1 000 funct3 rd dest 0010011 opcode |
R[rd] = R[rs1] + imm |
| LW | I-Type |
imm[11:0]
offset (12) rs1 base 010 funct3 rd dest 0000011 opcode |
R[rd] = M[R[rs1] + imm] |
| SW | S-Type |
imm[11:5]
imm (7) rs2 src rs1 base 010 funct3 imm[4:0] imm (5) 0100011 opcode |
M[R[rs1] + imm] = R[rs2] |
| BEQ | B-Type |
imm[12|10:5]
imm (7) rs2 src2 rs1 src1 000 funct3 imm[4:1|11] imm (5) 1100011 opcode |
if(rs1==rs2) PC += imm |
| JAL | J-Type |
imm[20|10:1|11|19:12]
imm (20) rd dest 1101111 opcode |
R[rd] = PC+4; PC += imm |
| JALR | I-Type |
imm[11:0]
imm (12) rs1 base 000 funct3 rd dest 1100111 opcode |
R[rd] = PC+4; PC=R[rs1]+imm |
| LUI | U-Type |
imm[31:12]
imm (20) rd dest 0110111 opcode |
R[rd] = {imm, 12'b0} |